Memory controller for a memory device
US12321190B2 · kind B2 · utility
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12References
16Claims
0Family size
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Key dates
| Filing date | Jun 22, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jun 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for a memory device, the memory controller including: a command generator configured to generate a command signal based on a system clock signal, and to generate phase difference information for the command signal; and a memory interface configured to receive the command signal and the phase difference information from the command generator, to adjust a timing of the command signal based on the phase difference information, and transmit the command signal of which the timing is adjusted as a timing adjusted command signal to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.