Method and apparatus for monitoring a PCIe NTB
US12321217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jan 13, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pair of compute nodes, each having a separate PCIe root complex, are interconnected by a PCIe Non-Transparent Bridge (NTB). An instance of a NTB monitoring process is started for each root complex, and the CPU affinity of the NTB monitoring processes are set to cause each NTB monitoring process to be executed on CPU resources of each respective CPU root complex. The NTB monitoring process on a given root complex is allowed to sleep until a triggering event occurs that causes the NTB monitoring process to wake and determine the state of the NTB. One such triggering event is a failure of an atomicity algorithm on the compute node to obtain a lock on peer memory in connection with implementing an atomic read operation on the peer memory over the NTB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.