Multi-core processor debugging systems and methods
US12321247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2020 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Apr 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2242
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates efficient and effective information storage device operations. In one embodiment, a system comprises: a plurality of processing cores configured to process information and a debug system coupled to the plurality of cores. The plurality of processing cores are configured to perform respective test operations on the respective processing cores. The debug system is configured to gather results of the test operations on a flexible compaction basis, wherein a compacted indication of a passing test result is available at a debug cluster basis and compacted indications of a failed test result available at the debug cluster basis are further resolved to identify a failing processing core within the cluster. The processing cores are organized in clusters, wherein a set comprising more than one of the plurality of processing cores and less than all of the processing cores is considered a cluster. The processing cores can be organized in levels, wherein the number of processing cores in a cluster differs at different level. The different levels correspond to a debug hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.