Distributed system level cache
US12321271B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 29, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Sep 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and a method of obtaining data for a processor are provided. The processor comprises at least a first core, a second core, and a distributed cache. The distributed cache comprises a first cache slice connected to the first core and a second cache slice connected to the second core and to the first cache slice. The first cache slice is configured to receive a memory access request from the first core and forward the memory access request to the second cache slice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.