Communication interface controller with output monitoring
US12321293B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Nov 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.