Lossless tiling in convolution networks—data flow logic
US12321843B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 21, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jan 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes memory and reconfigurable processors, operatively coupled to the memory, configured to execute a sequence of subgraphs of a graph. The sequence of subgraphs includes a preceding subgraph and a succeeding subgraph. The data processing system also includes data flow logic, operatively coupled to the reconfigurable processors and the memory, configured to store a tiled output of the preceding subgraph as a composed input in the memory and make available parts of the composed input for processing by the succeeding subgraph.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.