Single-clock display driver
US12322322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Dec 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the description provide for a circuit. In at least some examples, the circuit includes a driver. The driver includes a phase-locked loop and a digital interface. The phase-locked loop is configured to receive a clock signal and provide a second clock signal based on the first clock signal. The digital interface is configured to, receive the first clock signal, receive and sample data from a data frame at sequential rising edge transitions and falling edge transitions of the first clock signal, extract a portion of the data frame addressed to the driver from the data frame, and provide a portion of the data frame remaining after extracting the portion of the data frame addressed to the driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.