Memory chip and memory system including the same
US12322437B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Oct 30, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory chip includes a plurality of storage blocks respectively including a plurality of memory cells; and a logic circuit configured to control the plurality of storage blocks, wherein the logic circuit includes an input/output pad configured to input data to the plurality of storage blocks and output data to the plurality of storage blocks; wherein the logic circuit is further configured to allocate block address codes having a bit inversion relationship with each other, output a mode selection signal in response to external control, output an external address code in response to the mode selection signal indicating a first addressing mode, and output an address code having a bit inversion relationship with regard to the external address code in response to the mode selection signal indicating a second addressing mode, and select a storage block to be controlled by the access command from among the plurality of storage blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.