Programmable memory and method for driving programmable memory
US12322462B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jul 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory includes a plurality of antifuse cells, a plurality of word lines and a control circuit. The plurality of antifuse cells are arrayed along row and column directions, herein each of the plurality of antifuse cells includes an antifuse and a switching transistor, a first end of the antifuse being connected to a first terminal of the switching transistor. Each of the plurality of word lines is connected to gates of the switching transistors located in a same row. The control circuit is connected to the plurality of word lines, and is configured to provide a first voltage to a word line connected to a target antifuse cell in a program mode, and provide a second voltage to the word line connected to the target antifuse cell in a read mode, herein the first voltage is greater than the second voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.