Array substrate and display device
US12322736B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 31, 2021 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | May 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate (100) and a display device. The array substrate (100) includes a bonding area (102). The array substrate (100) includes a substrate (10), a first conductive layer (20) on the substrate (10), a first insulating layer (30) on one side of the first conductive layer (20) away from the substrate (10), and a second conductive layer (40) on one side of the first insulating layer (30) away from the substrate (10). The bonding area (102) is provided with bonding pins (201), and the bonding pin (201) includes a first conductive portion (21) and a second conductive portion (41) located on the side of the first conductive portion (21) away from the substrate (10), the first conductive portion (21) is located in the first conductive layer (20), the second conductive portion (41) is located in the second conductive layer (40), and the first conductive portion (21) is in direct contact with the second conductive portion (41). The first insulating layer (30) is provided with at least one first opening (301), and the orthographic projection of each of the first openings (301) on the substrate (10) covers the orthographic projections of the plurality of bonding pins (201) on the s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.