Integrated power management cells for gate all around technologies
US12323142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jan 25, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
At least one integrated power management cell of an IC includes a first cell, which is a 4-height cell, that includes a first continuous n-well, a first power interconnect coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well, a second continuous n-well, a second power interconnect coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well, a first subset of a first voltage level shifter associated with the first voltage domain and coupled to the first power interconnect, and a second subset of the first voltage level shifter associated with the second voltage domain and coupled to the second power interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.