Glitch-free zero-latency AGC for sigma delta modulator
US12323166B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jan 31, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system, comprising: a sigma-delta modulator using an integrator of a cascade-of-integrator feedback topology to perform operations is disclosed. The operations can comprise in response to receiving a gain value, applying the gain value to a group of feed-forward coefficients, determining a change in the gain value, and adjusting, during a clock cycle of a defined time period, a plurality of state variables of the sigma-delta modulator by multiplying each of the state variables by the scale factor that is a ratio of the gain value after determining the change in the gain value the gain value before determining the change in the gain value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.