Memory and method for forming same
US12324141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Dec 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A method for forming a memory includes the following operations: a substrate and a semiconductor layer located on the substrate are formed; the semiconductor layer is patterned to form a plurality of first isolation structures and channel regions, each first isolation structure includes a first through hole and a second through hole, and a first isolation pillar located between the first through hole and the second through hole; a first filling layer filling up the first through hole and the second through hole is formed; the first isolation pillar is removed to form a third through hole located in the first filling layer; a barrier layer filling up the third through hole is formed; the channel regions are exposed by removing the first filling layer; and a gate layer covering surfaces of the channel regions is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.