Semiconductor device and layout method of the same
US12324246B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 18, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Sep 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device according to an embodiment of the present inventive concept includes a plurality of standard cells in a first direction and a second direction, parallel to an upper surface of a substrate and intersecting with each other, and each of the plurality of standard cells having one or more gate structures and one or more active regions, and in some standard cells providing the same circuit and in standard cell regions at different locations, input lines or/and output lines are at different locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.