Contaminated interface mitigation in a semiconductor device
US12324301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2021 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jan 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/6572
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor device comprises a substrate, a first hole-transporting layer over the substrate, a first electron-transporting layer on the first hole-transporting layer, and a second hole-transporting layer over the first electron-transporting layer. At least one of the first electron-transporting layer and the second hole-transporting layer has an organic component. The device is characterized by one of the following: a metal oxide layer present on the first electron-transporting layer, wherein a second electron-transporting layer is on the metal oxide layer, wherein the second hole-transporting layer is on the second electron-transporting layer, or the second hole transporting layer has a first p-doped hole-transporting surface present on the first electron-transporting, layer and a second p-doped hole-transporting surface facing away from the first p-doped hole-transporting surface, or the first electron-transporting layer is on a top surface and on sidewalls of the first hole-transporting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.