Instruction scheduling method, instruction scheduling apparatus, device and storage medium based on durations consumed by memory access instructions during instruction running scenarios
US12327121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2022 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Oct 18, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure disclose an instruction scheduling method, an electronic device and a storage medium. The method comprises: determining at least one target memory access instruction in an instruction set corresponding to a micro-architecture model; determining durations consumed by each target memory access instruction in a plurality of instruction running scenarios; and, performing instruction scheduling on each target memory access instruction on the basis of the durations consumed by each target memory access instruction in the instruction running scenarios. By using the embodiments of the present disclosure, memory access instructions can be scheduled on the basis of the durations consumed by the memory access instructions in different instruction running scenarios, so that the applicability is high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.