Memory controller that transmits hammer addresses with different command protocols and memory system including the same
US12327583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2022 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Jul 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/0657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller to control a semiconductor memory device, includes a row hammer management circuit and a scheduler. The row hammer management circuit counts each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and determines a hammer address associated with at least one memory cell row which is intensively accessed among from the plurality of memory cell rows and a type of the hammer address associated with an urgency of management of the hammer address based on the counting values. The scheduler transmits the hammer address to the semiconductor memory device according to a different command protocol based on the type of the hammer address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.