Semiconductor storage device
US12327596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2021 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Apr 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory of an embodiment includes: a memory cell array including a plurality of memory cell transistors; a plurality of word lines connected to a plurality of gates of the plurality of respective memory cell transistors; a VPGM monitor connected to at least one of the plurality of word lines; and a sequencer. When writing voltage is applied to a selected word line selected from among the plurality of word lines at data writing to the memory cell array, the sequencer detects voltage of the selected word line through the VPGM monitor and determines whether detected voltage obtained through the detection has reached a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.