Memory with error checking and correcting unit
US12327600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2023 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Dec 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.