ZQ calibration circuit, operation method of the ZQ calibration circuit, and semiconductor memory device
US12327603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2023 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Sep 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ZQ calibration circuit included in a semiconductor memory device includes a reference voltage selector configured to output a reference voltage selected from among a first reference voltage and a second reference voltage generated based on a first supply voltage and a second supply voltage, in response to a selection signal, a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage, and a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is toggled. Levels of the first and second reference voltages are different from each other, smaller than a level of the first supply voltage, and greater than a level of the second supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.