Stacked semiconductor device
US12327818B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2021 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Aug 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stacked semiconductor device encompasses an upper semiconductor substrate, an upper insulating film laminated on a principal surface of the upper semiconductor substrate, an upper sealing-pattern orbiting along a periphery of the upper insulating film, a lower chip defining a chip mounting area in at least a part of a principal surface, the principal surface is facing to the upper insulating film, and a lower sealing-pattern disposed on the principal surface of the lower chip, delineating a pattern mating to a topology of the upper sealing-pattern, orbiting around the chip mounting area, configured to implement a metallurgical connector by solid-phase diffusion bonding to the upper sealing-pattern. Hermetical sealed space is established in an inside of the chip mounting area, the upper insulating film and the metallurgical connector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.