Method of processing layered structures
US12327840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2020 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Mar 27, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of processing a stack of layers to provide a stack of discrete layer elements, comprises the steps of: providing a stack of layers comprising: #a first layer (20) provided by a first material; #a third layer (16) provided by a solid electrolyte; and #a second layer (18) located between the first and third layers, the second layer having a thickness of at least 500 nm and being provided by a second material comprising at least 95 atomic % amorphous silicon; removing a through-thickness portion of the first layer (20) to form a first discrete layer element (20a) provided by the first material; removing a through-thickness portion of the second layer (18) to form a second discrete layer element (18a) provided by the second material, the second discrete layer element being located between the first discrete layer element (20a) and the solid electrolyte; and etching the third layer (16) using the second discrete layer element (18a) as an etching mask, to form a third discrete layer element (16a) provided by the solid electrolyte; wherein the first, second and third discrete layer elements provide the stack of discrete layer elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.