Non-overlapping generation technique for bootstrap switches
US12328112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2023 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Jun 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes a bootstrap circuit having an input and an output. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit, a second transistor, and a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor. The system also includes a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.