Optimization of edge computing distributed neural processor for wearable devices
US12328649B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Oct 21, 2019 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Aug 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and/or methods may include an edge-computing distributed neural processor to effectively reduce the data traffic and physical wiring congestion. A local and global networking architecture may reduce traffic among multi-chips in edge computing. A mixed-signal feature extraction approach with assistance of neural network distortion recovery is also described to reduce the silicon area. High precision in signal features classification with a low bit processing circuitry may be achieved by compensating with a recursive stochastic rounding routine, and provide on-chip learning to re-classify the sensor signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.