Transistor, 3D memory and manufacturing method therefor, and electronic device
US12328863B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2023 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Apr 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.