Semiconductor devices
US12328866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2023 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Sep 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
Abstract
Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.