Semiconductor device
US12328870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2022 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | May 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A semiconductor device may include a substrate including a cell region and a peripheral region, lower electrodes on the cell region of the substrate, a dielectric layer on surfaces of the lower electrodes, a silicon germanium layer on the dielectric layer, a metal plate pattern and a polishing stop layer pattern stacked on the silicon germanium layer, and upper contact plugs physically contacting an upper surface of the silicon germanium layer. The upper contact plugs may have an upper surface farther away from the substrate than an upper surface of the polishing stop layer pattern. The upper contact plugs may be spaced apart from the metal plate pattern and the polishing stop layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.