Semiconductor device and electronic system including the same
US12328875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2021 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | May 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. The device includes a substrate, a cell array structure provided on the substrate to include a plurality of stacked electrodes spaced apart from each other, an uppermost one of the electrodes being a first string selection line, a vertical channel structure provided to penetrate the cell array structure and connected to the substrate, a conductive pad provided in an upper portion of the vertical channel structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a cutting structure penetrating the first string selection line. The cutting structure penetrates a portion of the conductive pad. A bottom surface of the bit line contact includes first and second bottom surfaces in contact with the conductive pad and the cutting structure, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.