Silicon-on-insulator (SOI) device having variable thickness device layer and corresponding method of production

US12328891B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Manoj Chandrika Reghunathan · Kulim, MY
• Devesh Kumar Datta · Singapore, SG
• Eric Graetz · Klagenfurt, AT
• Muhammad Akmal Hasanudin · Kapar, MY
• Vijay Anand Ramadass · Kampung Bukit Kechil, MY

Key dates

• Filing date: Aug 30, 2022
• Grant date: Jun 10, 2025
• Expiry date: Jul 1, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.