Circuit and method to measure simulation to silicon timing correlation
US12332305B2 · kind B2 · utility
0Cited by
15References
5Claims
0Family size
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Key dates
| Filing date | Nov 10, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Nov 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/134
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit includes a programmable delay path comprising a plurality of path delay tuners configured to receive a plurality of control signals and add to the programmable delay path an amount of cell delay and an amount of wire delay that are based on the plurality of control signals. The integrated circuit further includes a controller configured to provide the plurality of control signals to the programmable delay path, receive a signal from the programmable delay path, and compare the signal to a reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.