Synchronous reset deassertion circuit
US12332683B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Aug 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.