Processing wakeup requests in a processing system having power management circuitry and a processing circuitry
US12332724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Feb 22, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.