Electronic device having a plurality of chiplets
US12332810B1 · kind B1 · utility
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18Claims
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Key dates
| Filing date | Nov 6, 2024 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Nov 6, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is an electronic device, including a first chiplet including a first bus interface, a first interconnect management module, and a first interconnect module, and a second chiplet connected to the first chiplet through the first interconnect module, wherein, in response to an occurrence of a request transaction associated with the second chiplet, the first interconnect management module stores, in a register, first information associated with the request transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.