Method and apparatus for performing address translations using a remapping process
US12332820B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2022 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Feb 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the subject disclosure may include, for example, remapping a first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines, the first remapped address bus supplying updated address information, connecting the first address remapped bus to an address translation unit (ATU), the ATU configured to translate the updated address information into translated address information supplied to a second address bus, and remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the second remapped address bus changing the translated address information into updated translated address information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.