Estimating a scaled cost of implementing an operation unit graph on a reconfigurable processor
US12332836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Aug 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.