Processing device using heterogeneous format input
US12333271B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2024 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Sep 20, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device comprises multiplier circuitry configured to output a product of mantissas represented by first and second signals in response to a mode signal and output a product of an integer represented by the first signal and a mantissa represented by the second signal in response to the mode signal. The processing device further includes an aligning circuit configured to shift a mantissa part of a third signal based on an exponent part of the third signal and an exponent of a product of the first and second signal to generate and output a shifted signal. The processing device further includes an arithmetic logic circuit configured to output a mantissa of a sum of a product of the first and second signals and the third signal in response to an output signal of the aligning circuit and an output signal of the multiplier circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.