Data-type-aware clock-gating
US12333274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2020 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Aug 3, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To reduce power consumption, data bits or a portion of a data register that is not expected to toggle frequently can be grouped together, and be clock-gated independently from the rest of the data register. The grouping of the data bits can be determined based on the data types of the workload being operated on. For a data register configured to store a numeric value that supports multiple data types, the portion of the data register being clock-gated may store a group of data bits that are unused for one or more data types of the multiple data types supported by the data register. The portion of the data register being clock-gated can also be a group of data bits that remain unchanged or have a constant value for numeric values within a certain numeric range that is frequently operated on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.