Iterative compilation to optimize translation in reconfigurable dataflow architectures
US12333283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jul 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method a compiler performs a trial compilation to a low level (LL) intermediate representation (IR) of a high level (HL) decision to execute a dataflow application on a computing system. The LLIR comprises hardware resources to execute the application based on the HL decision and the compiler determines a trial result based on LL execution metrics associated with the trail compilation. The compiler performs a trial compilation of a second HL decision to a second LLIR and determines a trial result based on LL execution metrics associated with the second trail compilation. The compiler evaluates the trial results and, based on the evaluations, selects one or both of the HL decisions for executing the dataflow application. A computer program product and a computing system can implement the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.