Cooperative group arrays
US12333311B2 · kind B2 · utility
Assignee
Inventors
- Greg Palmer
- Gentaro Hirota
- Ronny Meir Krashinsky
- Ze Long
- Brian Pharris
- Rajballav DASH
- Jeff Tuckey
- Jerome F. Duluk, Jr.
- Lacky V. Shah
- Luke Durant
- Jack Choquette
- Eric S. Werness
- Naman GOVIL
- Manan Patel
- Shayani DEB
- Sandeep Navada
- John H. Edmondson
- Prakash BANGALORE PRABHAKAR
- Wish Gandhi
- Ravi Manyam
- Apoorv Parle
- Olivier Giroux
- Shirish Gadre
- Steve HEINRICH
Key dates
| Filing date | Mar 10, 2022 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Sep 7, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.