Synchronization of processing elements that execute statically scheduled instructions in a machine learning accelerator
US12333351B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Apr 17, 2020 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Oct 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and apparatus are disclosed herein for bridging a deterministic phase of instructions with a non-deterministic phase of instructions when those instructions are executed by a machine learning accelerator while executing a machine learning network. In the non-deterministic phase, data and instructions are transferred from off-chip memory to on-chip memory. When the transfer is complete, processing elements are synchronized and, upon synchronization, a deterministic phase of instructions is executed by the processing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.