Feedforward compensation of high-luminance banding Mura compensation
US12333995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2024 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Mar 5, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/16
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein provide various apparatuses and techniques to efficiently mitigate front-of-screen (FoS) artifacts that may occur due to voltage fluctuations due to alternating current (AC) or direct current (DC) mechanisms that may occur in a variety of pixel types. In one embodiment, emission profile awareness circuitry may be implemented to mitigate for FoS artifacts due to DC mechanisms. Two-dimensional (2D) digital compensation circuitry may address the DC portion of the voltage fluctuations by accounting for an emission profile applied to content displayed on an electronic display. In some embodiments, the 2D digital compensation circuitry may compensate for the AC portion of the voltage fluctuations by duplicating the AC voltage fluctuations via voltage error subtraction circuitry and voltage error accumulation circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.