Memory device having merged banks on substrate, and method for operating memory device
US12334139B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 9, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Feb 21, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes one or more memory blocks. Each memory block includes a plurality of first sense amplifier circuits, a plurality of row segments, and a plurality of row decoders. The row segments and the first sense amplifier circuits are arranged alternately along a first direction. Each row segment includes a plurality of memory cells arranged in rows and columns. Each column of memory cells extends in the first direction. The row segments are divided into N groups of row segments, and N is greater than one. The row decoders are coupled to the row segments respectively, and divided into N groups of row decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.