Operating and testing semiconductor devices
US12334170B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 9, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Aug 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation method of a memory device includes programming a test pattern in a normal area, obtaining locations of error bits with respect to the test pattern and an error count for each error bit location, and repairing faulty cells included in the normal area with redundancy cells in a redundancy area based on the locations of the error bits and the error counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.