Memory device, memory system and method for operating memory system including command and address training
US12334186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jun 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory system including: a memory device; and a memory controller configured to transmit a command and address (CA) signal and a data clock (WCK) signal to the memory device, and transmitting a data (DQ) signal to the memory device or receive the DQ signal from the memory device. The memory device may include a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal, a CA sampler configured to sample the CA signal based on the first division clock signal, and a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and the memory controller may include processing circuitry configured to enter CA training in response to receiving the parity error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.