Chip packaging structure and related inner lead bonding method
US12334470B2 · kind B2 · utility
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2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jun 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81805
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.