Clock data recovery circuit of display and clock recovery circuit thereof
US12334935B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2024 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | May 20, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock data recovery circuit of a display suitable for recovering a clock from a clock data signal. The clock data recovery circuit includes a clock recovery circuit configured to delay an input clock through delay units of multiple stages, and output delayed clocks from the delay units, respectively; and a data recovery circuit configured to recover data of a clock data signal using a recovered clock selected among the delayed clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.