Semiconductor structure and method for manufacturing semiconductor structure
US12336164B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2022 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jul 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0335
Abstract
A semiconductor structure includes: a base including bit lines arranged at intervals and semiconductor channels arranged at intervals, bit lines extending in first direction, semiconductor channels being located at part of top surfaces of bit lines, each semiconductor channel including first area, second area, and third area arranged successively in a direction perpendicular to top surfaces of bit lines; dielectric layers located between adjacent bit lines and located on side walls of semiconductor channels; gate electrodes surrounding dielectric layers in second area and extending in second direction; metal semiconductor compound layers located on top surfaces of semiconductor channels; diffusion barrier layers at least surrounding side walls of metal semiconductor compound layers; and insulating layers located between adjacent semiconductor channels on same bit line and isolating gate electrodes and diffusion barrier layers on each dielectric layer from gate electrodes and diffusion barrier layers on dielectric layers adjacent to each dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.