Solid-state drive with multimode compression and error correction
US12339745B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2024 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Apr 22, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for providing compression and error correction coding (ECC) in a solid-state drive (SSD). A method is provided that includes: determining whether a data item is to be written to flash memory using a general-purpose mode or a zero-padding mode: in response to a determination that a data item is to be written into flash memory using the zero-padding mode: padding the data item with an all-zero tail to form an LBA data block of a predefined size; performing ECC coding on the LBA block to generate an ECC codeword; removing the all-zero tail from the ECC codeword to generate a shortened ECC codeword; and storing the shortened ECC codeword in flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.