Method for error injection, electronic device, and computer program product
US12339757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2023 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Jul 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error injection technique involves: receiving a logic error including an injection address parameter and an injection error parameter, and matching the injection address parameter in the logic error with a request address parameter in a response to a data request in at least one workflow. The technique further involves: in a case that the injection address parameter is matched with the request address parameter, injecting the injection error parameter into the response to the data request. Such a technique provides a flexible error injection mode, which may fully test the reliability and availability of storage devices, thereby providing high-quality storage services for users.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.