Optimizing space and time of operations for register configurations
US12339772B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2023 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Dec 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Presented herein are systems and methods for configuring devices with write operations. One or more processors can identify a first sequence of write operations to configure a device. Each write operation in the first sequence of write operations can identify a set of a value and an address to which to write the value. The one or more processors can determine one or more distances between a set of the value and the address of a write operation and at least one other set of the value and the address of one or more other write operations in the first sequence of write operations. The one or more processors can generate a second sequence of write operations based at least on the one or more distances. The one or more processors can cause the device to be configured using the second sequence of write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.